
--compile vhdl file
acom -reorder -dbg -incr -work test2 -2008  $dsn/src/test2.vhd

--compile verilog file
alog -dbg -sve -incr   -work test2 $dsn/src/test1.v

--initiallize simulation
asim -advdataflow  top

--add signal to waveform
--wave  
wave /top/DUT/alpha
wave /top/DUT/beta
wave /top/DUT/zeta
wave /top/DUT/clk
wave /top/DUT/reset
wave /top/DUT/din
wave /top/DUT/dout
--run sim
run 500 ns

--end sim
endsim
